Skillset required : HDLs

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 Skillset required for career in VLSI

What Is Hardware Description Language(HDL)? 

      With the advent of VLSI Technology, designers could design single chips with more than 100,000 transistors. Thus it is not possible to verify such circuits physically Computer aided  techniques became critical for verification and design of VLSI circuits. As the design got more complex, logic simulation assumed an important role in the design process. Thus came in the Hardware Description Languages. Designers  could remove the bugs in the architecture before the chip was designed further with HDLs. Designs can be described at a very abstract level by the use of HDLs .Designers can write their are RTL description without a specific fabrication technology. Logic synthesis tools automatically convert the design into any fabrication technology. Also functional verification of the design can be done early in the design cycle.

Introduction to Verilog HDL:

      Verilog is understood as a shorthand for describing digital hardware or a general- purpose hardware description language. Verilog was developed by Gateway Design Auto  in 1984 as a proprietary language for logic simulation. Gateway was acquired by Cadence later and Verilog was made open standard. There are two general types of description :behavioral and structural. Structural Verilog describes how a module is composed of simpler modules or basic primitives such as gates or transistors. Behavioral Verilog describes how outputs are  computed functions of the inputs. 

Is Verilog so popular?

1 .It is very similar to C programming language designers with C programming experience find it  easy to learn Verilog.

2.It allows different levels of abstraction to be mixed in the model.  Thus a designer can define hardware model in terms of Switches, gates, RTL or behavior code.

3.It has a powerful feature called as Programming Language Interface(PLI)  which allows the user to  write custom C code to interact with the internal Data structures of Verilog.

SystemVerilog

      SystemVerilog is a combination of both Hardware Description Language (HDL) and Hardware Verification Language (HVL) and combined termed as HDVL. It describes the structure and behavior of electronic circuits as well as it verifies the electronic circuits written in a Hardware Description Language. SystemVerilog acts as a superset of Verilog with a lot of extensions to Verilog.


Verilog

SystemVerilog

HDL

HDL+HVL

IEEE 1364.

IEEE 1800-2012.

It was began in 1983 as proprietary language for hardware modelling.

It was originally intended as an extension to Verilog in the year 2005.

Used to structure and model electronic systems.

Used to model, design, simulate, test and implement electronic system

It supports structured paradigm.

It supports structured and object oriented paradigm.

Influenced by C language and Fortran programming language.

Based on Verilog, VHDL and C++ programming language.

It has file extension .v or .vh

It has file extension .sv or .svh


It supports Wire and Reg datatype.

It supports various data types like enum, union, struct, string, class

It is based on a hierarchy of modules.

It is based on classes.

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