Open source tools for IC design and Simulations

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In this blog we will understand the various IC design components and open source tools available to perform IC design. First lets take a look at  IC design components. 


Fig: Logic Synthesis

First step in IC design is to do Logic Synthesis. Logic synthesis is a process by which an abstract specification of desired circuit behavior which is the netlist, at register transfer level (RTL), is converted or transformed into a design implementation in terms of logic gates. And the open source tool which helps us do logic synthesis is Yosys Open Synthesis Tool.

Fig: Floor-planning



Second step is Floorplanning. In floorplanning blocks/macros in the chip/core area, are placed . Floor-plan determines the size of die and creates wire tracks for placement of standard cells. It. creates power ground(PG) connections.

         

Fig : Placement and Clock Tree Synthesis


Third Step is Placement of logical cells that we got from first step and third step is CTS Clock tree Synthesis CTS is the process of providing clock to all the clock pins of sequential circuits by using inverters/buffers for balancing the skew and to minimizing the insertion delay. For these three steps we require Graywolf which is another open source software used for IC design.


Fig: Routing

Fourth Step is Routing ,in  this stage the interconnections are made by determining the precise paths for each nets. For doing this process of routing there is a tool Qrouter.


And there is a need to do Static timing analysis after every step. STA is for verifying the timing performance of a design by checking all possible paths for timing violations under worst case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit. This can be done using Opentimer


To view the layout created at every stage we need a layout viewer. Magic is a software that can be used for Layout viewing.


Also  there is NGSpice where users can give a netlist and analyse the output waveforms. Users can compare pre-layout spice simulation output waveform and  post-layout spice simulation output waveform. For analyzing the impact of parasitic capacitances and so on Ngspice can be used.

Finally ESim is a schematic editor, it is an open source EDA tool for circuit design, simulation, analysis and PCB design.

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